Project

The BMBF joint project NEUROTEC aims to realise technology for novel neuromorphic electronic hardware and the corresponding software. An essential key component is the memristive cell based on various physical memory mechanisms. It stores information in electrical resistance and retains its digital or even analogue memory value even in a de-energised state. In addition to the fundamental research in the work packages, the technology is to be demonstrated in the project as a process chain that produces a series of demonstrator circuits. The cooperating system manufacturers and companies in the field of measurement technology will be familiarised with the new concepts, materials and hardware components of neuromorphic electronics. This is being done in the expectation that there will be a growing global market for neuromorphic electronics in 5-10 years. These companies are all based in the Rhineland region. The NEUROTEC project is thus making a contribution to structural change in the field of digitalisation and strengthening high technology. Further specification and applications of the AI chips will be researched in the NeuroSys future cluster. The common vision of both projects is to create an economic ecosystem in the field of neuromorphic AI hardware and software in the Aachen-Jülich region.

WP1

WP2

WP3

WP4

WP5

WP6

WP1 Material development for memristive cells

Memristive devices, storing information in their electrical programmable, con-figuration-dependent resistance states, act as the fundamental building blocks for energy-efficient neuromorphic com-puting. In WP1, various memristive concepts are explored. These include VCM-type metal oxides, PCM-type transition metal chalcogenides, and the new 2D-layered materials such as transition metal dichalcogenides. Device fabrication is focused on compatibility with silicon chips.

WP2 Component integration and 3D studies

Different integration architectures starting from passive memristive cross-bar matrices, over 1T1R configurations of memristive devices towards highly connective 3D integration are explored in WP2. Not only are CMOS back-end-of-line devices examined, but front-end-of-line devices with ferro-electric field-effect transistors are also under investigation. Moreover, CMOS struc-tures are designed to study the properties of 2D materials and their switching characteristics.

WP3 Simulation and modeling

Physical models of material properties and memristive switching mechanisms establish the foundation for compact models in circuit design. WP3 completes the cycle of material tuning for improved devices, transitioning the description of innovative devices towards electronic design automation, thereby enabling circuit simulation. The development process includes both virtual prototypes and hybrid virtual-physical prototypes.

WP4 Measurement and test technology for neuromorphic electronics

The objective involves measurement, analysis and tuning of the switching behaviors of fast single memristive cells and 32x32 matrices used for vector-matrix-multiplication. Needle-probe devices on automated probe stations generate statistics for yield, variability, and endurance tests. Additionally, fault models for a future series production of memristive devices are investigated.

WP5 Concepts for neuromorphic circuits

The neuromorphic circuit concepts explored are computing in memory accelerators, ternary content addressed analog memory, artificial neural network architectures, pro-babilistic computing building blocks such as physical unclonable functions and true random number generators. Hardware security issues are addressed. The ultimate goal is a neuromorphic + classical Design-Tech-nology-Co-Optimization.

WP6 Hardware-software integration for neuromorphic systems

The applications investigated in WP6 include currently popular AI models, including attention mechanisms and spatiotemporal pattern learning. Attentional mechanisms will utilize CIM blocks for the required matrix operations, and TCAM blocks as memory modules. Spatio-temporal pattern learning will employ the memristor-based SNN chip of WP5.

K1 MOCVD system technology for 2D materials

AIXTRON S.E. industrializes the metal-organic vapor deposition of 2D material sytems. The focus is on scaling towards homogeneous material deposition on 200- and 300-mm wafers.

K2 Large scale laser deposition of memristive oxides

SURFACE systems + technology develops pulsed laser deposition tools for homogenous large scale material deposition of area dependent switching VCM devices. In addition to serving the R&D market there is an opportunity for industrialization of PLD for small series production.

K3 Test system for neuromorphic memory

aixACCT systems and AMOtronics, are working to optimize the matrix tester for versatile high throughput set and measurement routines. AMOtronics is focused on improving the performance of ADC and DAC performance. Meanwhile, aixACCT systems targets the implementation of artificial intelligence-based analysis and device quality control.

K4 Evaluation platform

AMOtronics is engaged in the deve-lopment of test and measurement boards that are specific to neuromorphic hardware. These boards are designed for the interfacing, programming, and evaluation of the demonstrator chips.

DP Demonstrator project

The demonstrator project binds all project activities towards functional demonstrators. Innovative memristive devices, integration architectures, neuromorphic circuits and fun-ctional AI blocks are realized on CMOS chips. The chips are bonded and interfaced to evaluation boards and combined with digital neuromorphic systems on a chip for programming, testing, and benchmarking.

Last Modified: 02.06.2024