WP2 Component integration and 3D studies

The realization of energy-efficient hardware solutions for neuromorphic computing requires not only suitable memristive materials but also new device concepts and circuit architectures and, associated with this, the development of suitable integration technologies. Within NEUROTEC, fundamental device, architecture and material integration technologies with different degrees of technological maturity are developed and researched. This opens up short-/mid- and long-term perspectives of utilization. A very important point here is to ensure the greatest possible compatibility with CMOS technology, which will enable a relatively simple and gradual technology transfer to industrial applications as soon as the appropriate level of maturity has been reached.

With the highest technological maturity level NEUROTEC addresses the integration of memristive materials in crossbar arrays on a CMOS platform. The goal here is to develop multilevel switching in CMOS technology for, for example, compute-in-memory operations for MNIST pattern recognition based on a 64x64 1T1R crossbar array. In addition, novel synaptic devices are also integrated into a CMOS platform. Thus, in addition to ferroelectric field-effect transistors consisting of two connected "back-to-back" silicide Schottky diodes switched via multi-domain polarization, HfO2-based threshold switches are also being investigated.

In order to realize synaptic networks with very high connectivity, ultra-compact, two-dimensional crossbar arrays and three-dimensional networks are being researched within the framework of NEUROTEC. Optimized damascene and wafer bonding processes are developed for the fabrication of such two- and three-dimensional networks. A main goal is the demonstration of a unit cell of a full 3D network consisting of a 3x3x3 electrode array, which allows the generation of filamentary interconnects with different weights between the electrodes.