Endurance of 2 Mbit Based BEOL Integrated ReRAM

Endurance of 2 Mbit Based BEOL Integrated ReRAM
Experimental endurance investigations of 2 Mbit ReRAM from a 16 Mbit test-chip (right inset). Evolution of current distribution after cycling shows overall great endurance. Number of few stuck-at-LRS fail-bits increases (left inset) up to approx. 10ppm after 500k cycles.
Copyright:
— RWTH Aachen

Nils Kopperberg and a team of authors from RWTH Aachen University and the Peter Grünberg Institute PGI-7 "Electronic Materials", together with their industrial cooperation partners from Infineon Technologies AG within a transfer project of the SFB 917 Nanoswitches, demonstrate in their latest publication "Endurance of 2 Mbit based BEOL integrated ReRAM " the reliability of memristive switching electronic devices (ReRAM Redox Random Access Memory) based on the so-called valence-switching mechanism. The devices were integrated on silicon CMOS at the end of the manufacturing process (back end of line) and underwent extensive testing in close collaboration with Dr. Stefan Wiefels (PGI-7). According to lead scientist Dr. Stephan Menzel (PGI-7), the few failures can be described using a model (Kinetic Monte Carlo - KMC model) and potentially controlled by improving the algorithms for driving the memory devices. The work lays crucial foundations for the manufacturability and application of ReRAM cells far beyond memory applications: Two ongoing projects, both funded by BMBF, the NEUROTEC project (headed by Prof. Rainer Waser) and the ZukunftsCluster NeuroSysProjekt A (Dr. Dirk Wouters, headed by Prof. Max Lemme) are exploring the use of ReRAM devices in novel hardware systems for neuromorphic computing with applications in AI and supercomputing.

Last Modified: 03.05.2024
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